This invention relates generally to the field of CMOS (complementary metal oxide semiconductor) technology and, more particularly, to a process which uses a single masking step to form self-aligned dual wells (tubs) and self-aligned field-doping regions in a CMOS structure forming a part of a semiconductor device, such as a field effect transistor.
In dual-well (twin-tub) CMOS technology, it is highly desirable to utilize as much of the semiconductor chip area as possible. In the past, several lithographic masking steps were required for making integrated circuit chips having densely packed elements and devices thereon, but each masking step inherently requires the dedication of chip areas which otherwise could be occupied by the devices ultimately formed in the chip. Also, in the past, the doping concentration of the dual wells and also of the field regions were dependent upon each other, and/or both P and N field isolation regions were doped with a conductivity-determining impurity of a first type, one region masked, and the other region doped with a conductivity-determining impurity of the opposite type to form the required P-doped and N-doped field isolation regions.
In forming field isolation regions between devices on a chip, it is necessary to provide field-doping beneath these isolation regions to provide electrical isolation between adjacent devices or active regions on the same substrate which is, typically, a lightly doped silicon wafer. The fabrication step or steps that produce these isolation regions affects the spacing between devices (i.e. the device packing density) on the chip, as well as the electrical characteristics of the device. The field-doping beneath the isolation regions is often referred to as a "parasitic channel stopper" doping, and it is used to control the parasitic MOS threshold voltages outside of the active region of a device, such as an FET, and to eliminate unwanted conduction due to inversion under the field isolation when lightly doped substrates are employed. There are many prior art techniques for aligning the field-doping to the field isolation. One technique is to use an extra lithographic masking step; however, the disadvantages of such an extra masking step have already been discussed. In order to form a recessed isolation oxide with a self-aligned field-doping, it is also known to provide an oxidation barrier layer, such as silicon nitride, for delineating the device regions. Thin silicon dioxide layers may be provided on either side of the silicon nitride layer to aid in its delineation and to prevent damage to the underlying silicon substrate. The photoresist pattern used to define the device regions also serves as the implantation mask, and the resist regions are located over the future device areas.
U.S. Pat. No. 4,144,101--Rideout discloses the broad concept of providing a self-aligned field-doping using only one lithographic masking step. It is important to employ as few masking steps as possible since the lithographic masking steps involved in preparing integrated circuits are among the most critical. Lithographic masking steps require high precision and registration and extreme care in execution. Each additional lithographic masking step in a process introduces possible masking defects and increases mask-to-mask registration problems that decrease the processing yield and, accordingly, significantly increases the fabrication cost. Although other factors affect the yield and cost, such as, for example, the number of high temperature heat treatments, a basic objective in FET integrated circuit fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of desired device structures. U.S. Pat. No. 4,144,101 discloses a process wherein the incorporation of the doping beneath the preselected isolation regions and the fabrication of the isolation regions require only a single lithographic masking step. More specifically, this patent discloses a process for providing ion-implanted doped regions in a substrate beneath preselected regions of an existing layer on the substrate, wherein the doped regions are self-aligned to preselected subsequently fabricated regions of the existing layer. The process includes providing a first layer of silicon dioxide on a silicon substrate. Ion-implanted doped regions are to be later formed beneath preselected portions of the oxide layer. A resist masking layer is formed on the oxide layer, and active impurities are ion-implanted through the oxide layer in those regions not covered by the resist masking material in order to provide ion-implanted regions beneath the oxide layer, whereby the resist and oxide layers act as a mask to prevent the implanted ions from penetrating therethrough. A lift-off material, such as aluminum, is deposited over the oxide layer and resist layer, and then the resist layer is removed, taking with it the lift-off material deposited on it. Then, the portion of the oxide layer which was beneath this layer is removed by etching, using the remaining lift-off material as a mask. Then, the remaining lift-off material is removed from the oxide layer beneath it, whereby there are obtained implanted regions in the substrate which are self-aligned at the edges to the boundaries of preselected fabricated regions of the oxide layer located above the ion-implanted regions. In other words, by the use of this lift-off technique, the masking pattern is actually reversed from over the device region before implantation, to over the field isolation region after implantation. After the formation of the field-doping regions which are self-aligned at the edges to the overlying isolation field oxide regions, further lithographic and ion-implantation steps are used to form the oxides, device-doping and conductors required to complete the fabrication of an FET having gate, source and drain regions. This lift-off technique is used in one embodiment of the present invention.
U.S. Pat. No. 4,435,896--Parrillo et al discloses a dual-well or twin-tub CMOS process using only a single lithographic masking step for forming self-aligned contiguous P- and N-wells. A silicon nitride layer and a silicon dioxide layer of different thicknesses are used to achieve this self-alignment of the wells; however, this patent does not address the problem of forming field-doping beneath field isolation regions.
U.S. Pat. No. 4,280,272--Egawa et al discloses a process of making a twin-well CMOS FET by using the conventional method of employing two masking steps to form spaced N- and P-wells.
U.S. Pat. No. 4,244,752--Henderson, Sr. et al discloses a process for making CMOS FET integrated circuits having both P-channel and N-channel structures, and in which only a P-channel well is formed. Both silicon dioxide and silicon nitride layers are formed on a P-type wafer to produce a silicon dioxide-silicon nitride sandwich, and a first masking step is used to etch away this sandwich to define the active areas of both the P-channel and N-channel devices to be formed later in those areas covered by the sandwich. A second masking step is used to form a photoresist pattern to enable ion-implantation to form a P-channel well. With the oxide-nitride sandwich serving as a mask, field-doping regions are formed by ion-implantation of a P-type dopant (boron). This implant goes into the field regions of both the N-channel well, where it is required, and the P-channel well where it is not desired. Field isolation oxides are then formed over the field-doping regions, using the silicon nitride layer as a mask to prevent oxidation of the active areas of the P-channel and N-channel devices.